Before measuring the efficiency of a simulator, one needs to check whether he has chosen the right hardware and software configuration.
The general guidelines for choosing HW & SW configuration which can increase the simulator performance are:
[1] Faster the processor, better performance. Multi-core processors can give more.
[2] L2 cache matters a lot for run-time
[3] Linux is better
[4] Opteron processors have built-in memory controller which helps simulators
[5] High speed disk drives like 10000 rpm would be very useful
[6] Fast DDR memory is critical
[7] Make sure that you have enough RAM so that the process does not swap - as it kills all performance.
[8] Large cache
Let us discuss about the various other factors that also affect the speed of the simulators in my next article.
Sunday, November 30, 2008
SIMULATORS - Are they really fast enough?
Week long regressions are the main concerns of CAD and verification engineers when they have to deliver the product on time and meet TTM.CAD team will always look for high speed simulators and demand EDA vendors to tune their software engine to meet their run time requirements.
By looking at the technology changes of processors, memories and OS, I would say EDA vendors should really come up with new innovative methods and technologies to make their simulators powerful enough to exploit these new features of the latest hardware and software technologies. For example, if the simulator is not capable of utilizing all the cores of a processor innovatively to execute parallel processes and reduce the run time, then there is no benefit of changing the technology, like single core processor to core duo. If the technology of the simulator is not changing, it might even treat your big servers and machines that have high-end processors as only your old desktop PC.
At the same time, one should also understand that updating the hardwares and softwares of the simulation form is highly needed to expect more out of simulators. CAD team has to work closely with the EDA vendors and understand about their technology road map. They have to guide the project teams to use the right version of the EDA tools, understand the flows and methodologies. This will really help the design and verification engineers to use the EDA tools to the full extent.
Do you know how much you are paying for the EDA tools? Are you utilizing the EDA tools efficiently?
I am really surprised about the fact that many of the semiconductor industries do not even have proper CAD teams. Especially in India, we think that CAD team is needed just for managing the licensing issues. In many organizations, IT guys do the license management. But IT team cannot replace CAD team and CAD engineers can do much more on jobs like evaluating EDA tools, methodologies, integrating various point tools and creating the design flow etc. They can actually guide their management team to choose their preferred EDA vendor.
In my next article, I am going to explain how you can tune your simulator engine and run it at its maximum speed.
By looking at the technology changes of processors, memories and OS, I would say EDA vendors should really come up with new innovative methods and technologies to make their simulators powerful enough to exploit these new features of the latest hardware and software technologies. For example, if the simulator is not capable of utilizing all the cores of a processor innovatively to execute parallel processes and reduce the run time, then there is no benefit of changing the technology, like single core processor to core duo. If the technology of the simulator is not changing, it might even treat your big servers and machines that have high-end processors as only your old desktop PC.
At the same time, one should also understand that updating the hardwares and softwares of the simulation form is highly needed to expect more out of simulators. CAD team has to work closely with the EDA vendors and understand about their technology road map. They have to guide the project teams to use the right version of the EDA tools, understand the flows and methodologies. This will really help the design and verification engineers to use the EDA tools to the full extent.
Do you know how much you are paying for the EDA tools? Are you utilizing the EDA tools efficiently?
I am really surprised about the fact that many of the semiconductor industries do not even have proper CAD teams. Especially in India, we think that CAD team is needed just for managing the licensing issues. In many organizations, IT guys do the license management. But IT team cannot replace CAD team and CAD engineers can do much more on jobs like evaluating EDA tools, methodologies, integrating various point tools and creating the design flow etc. They can actually guide their management team to choose their preferred EDA vendor.
In my next article, I am going to explain how you can tune your simulator engine and run it at its maximum speed.
Tuesday, November 25, 2008
Reusable Verification IPs [VIP]
SoC designs are very complex and generally they are composed of various pre-verified IPs. Most of the times the IP testbenches become useless at the full chip level. These IP TBs work only in the stand alone IP verification environment.
Why can't verification engineers build the SoC TB from IP TBs, especially when the design engineers can easily realize the SoC from IPs?
Let us consider the mobile chip. It has got the processor core IP, IP which implements the wireless communication, IPs for audio, video and entertainment applications etc. All these IPs have already been verified thoroughly using IP testbenches. One can easily plug-in all these IP TBs [VIPs] together and create the TB for the complete chip.
At the chip level, usually a top level environment is created. It includes all these VIPs and drives them as per the requirement. During simulation some of the VIPs will be active and some of them reactive. The top level env controls the active VIPs and triggers them in a particular order, like which one has to generate stimuli first, which one next etc. The monitors in the reactive VIPs still monitor the activities at the IP level.
I hope now you can visualize how the scenarios can be generated for the mobile chip verification using this technique. A typical scenario could be “Receiving calls while listening to music”.
Why can't verification engineers build the SoC TB from IP TBs, especially when the design engineers can easily realize the SoC from IPs?
Let us consider the mobile chip. It has got the processor core IP, IP which implements the wireless communication, IPs for audio, video and entertainment applications etc. All these IPs have already been verified thoroughly using IP testbenches. One can easily plug-in all these IP TBs [VIPs] together and create the TB for the complete chip.
At the chip level, usually a top level environment is created. It includes all these VIPs and drives them as per the requirement. During simulation some of the VIPs will be active and some of them reactive. The top level env controls the active VIPs and triggers them in a particular order, like which one has to generate stimuli first, which one next etc. The monitors in the reactive VIPs still monitor the activities at the IP level.
I hope now you can visualize how the scenarios can be generated for the mobile chip verification using this technique. A typical scenario could be “Receiving calls while listening to music”.
Thursday, November 20, 2008
SystemVerilog [SV]
What is SystemVerilog?
Let us first understand what is SV. SV is not something like a brand new hardware verification language. It's built on top of Verilog2001. All the Verilog language constructs seamlessly work with SV and vice-versa. In common man terms, one can say SystemVerilog is the latest version of Verilog HDL.
Why we need this language?
Basically HDLs are mainly for capturing RTL description of the design and they are not meant for verification. Some engineers wrongly assume that Verilog is good for verification and VHDL is good for RTL. I have seen some industries use VHDL only for TB. Actually both HDLs lack many constructs that you need for verifying complex designs.
Industries really need smart and powerful verification techniques to ship high quality chips and meet the TTM. Most of the designs are System On Chip[SoC] kind and very complex. Think of your mobile chip. It has to transmit and receive calls, play audio and video, support emails, games, internet etc. All these features have to be verified thoroughly at the IP level but not necessarily at the full chip level.
At SoC level, we do not want to spend more time on building the TB from the scratch. Here reusability is the key thing. How can we test the complete SoC using existing TBs of the IPs? How we are going to track the verification process? Project manager should be able update his management with the details like, how much done, how much more time required, allocating more resources …
I will talk about some prominent verification techniques in my next blog. I would like to take this mobile chip as an example and explore how these verification techniques/methodologies/technologies really help to accelerate the verification process and achieve high quality verification.
Let us first understand what is SV. SV is not something like a brand new hardware verification language. It's built on top of Verilog2001. All the Verilog language constructs seamlessly work with SV and vice-versa. In common man terms, one can say SystemVerilog is the latest version of Verilog HDL.
Why we need this language?
Basically HDLs are mainly for capturing RTL description of the design and they are not meant for verification. Some engineers wrongly assume that Verilog is good for verification and VHDL is good for RTL. I have seen some industries use VHDL only for TB. Actually both HDLs lack many constructs that you need for verifying complex designs.
Industries really need smart and powerful verification techniques to ship high quality chips and meet the TTM. Most of the designs are System On Chip[SoC] kind and very complex. Think of your mobile chip. It has to transmit and receive calls, play audio and video, support emails, games, internet etc. All these features have to be verified thoroughly at the IP level but not necessarily at the full chip level.
At SoC level, we do not want to spend more time on building the TB from the scratch. Here reusability is the key thing. How can we test the complete SoC using existing TBs of the IPs? How we are going to track the verification process? Project manager should be able update his management with the details like, how much done, how much more time required, allocating more resources …
I will talk about some prominent verification techniques in my next blog. I would like to take this mobile chip as an example and explore how these verification techniques/methodologies/technologies really help to accelerate the verification process and achieve high quality verification.
Wednesday, November 19, 2008
Change in the Verification World
In VLSI industries, everybody talks about SystemVerilog [SV]. We also find lot of job opportunities for the verification engineers who have working knowledge in SV. Students also look out for the VLSI design courses that focus more on verification and SV. They also strongly believe that SV knowledge is highly needed to get into industries.
Why so much noise about SystemVerilog? What is happening in the verification world?
I still remember, few years back everybody was talking about the hardware verification language 'e' and Specman. Industries used to search for the strings "e" and "Specman" in the resume. Cadence also acquired Versity to increase their market share in the verification. But now the VLSI industries are moving towards SV and migrating their legacy testbenches from the proprietary HVLs and HDLs to SV.
This change in the verification community clearly indicates that you always need to update yourself on the latest technology to maintain your market value, whether you are a student or an experienced verification engineer.
Why so much noise about SystemVerilog? What is happening in the verification world?
I still remember, few years back everybody was talking about the hardware verification language 'e' and Specman. Industries used to search for the strings "e" and "Specman" in the resume. Cadence also acquired Versity to increase their market share in the verification. But now the VLSI industries are moving towards SV and migrating their legacy testbenches from the proprietary HVLs and HDLs to SV.
This change in the verification community clearly indicates that you always need to update yourself on the latest technology to maintain your market value, whether you are a student or an experienced verification engineer.
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