SystemVerilog [SV]

What is SystemVerilog?

Let us first understand what is SV. SV is not something like a brand new hardware verification language. It's built on top of Verilog2001. All the Verilog language constructs seamlessly work with SV and vice-versa. In common man terms, one can say SystemVerilog is the latest version of Verilog HDL.

Why we need this language?

Basically HDLs are mainly for capturing RTL description of the design and they are not meant for verification. Some engineers wrongly assume that Verilog is good for verification and VHDL is good for RTL. I have seen some industries use VHDL only for TB. Actually both HDLs lack many constructs that you need for verifying complex designs.

Industries really need smart and powerful verification techniques to ship high quality chips and meet the TTM. Most of the designs are System On Chip[SoC] kind and very complex. Think of your mobile chip. It has to transmit and receive calls, play audio and video, support emails, games, internet etc. All these features have to be verified thoroughly at the IP level but not necessarily at the full chip level.

At SoC level, we do not want to spend more time on building the TB from the scratch. Here reusability is the key thing. How can we test the complete SoC using existing TBs of the IPs? How we are going to track the verification process? Project manager should be able update his management with the details like, how much done, how much more time required, allocating more resources …

I will talk about some prominent verification techniques in my next blog. I would like to take this mobile chip as an example and explore how these verification techniques/methodologies/technologies really help to accelerate the verification process and achieve high quality verification.