SoC designs are very complex and generally they are composed of various pre-verified IPs. Most of the times the IP testbenches become useless at the full chip level. These IP TBs work only in the stand alone IP verification environment.
Why can't verification engineers build the SoC TB from IP TBs, especially when the design engineers can easily realize the SoC from IPs?
Let us consider the mobile chip. It has got the processor core IP, IP which implements the wireless communication, IPs for audio, video and entertainment applications etc. All these IPs have already been verified thoroughly using IP testbenches. One can easily plug-in all these IP TBs [VIPs] together and create the TB for the complete chip.
At the chip level, usually a top level environment is created. It includes all these VIPs and drives them as per the requirement. During simulation some of the VIPs will be active and some of them reactive. The top level env controls the active VIPs and triggers them in a particular order, like which one has to generate stimuli first, which one next etc. The monitors in the reactive VIPs still monitor the activities at the IP level.
I hope now you can visualize how the scenarios can be generated for the mobile chip verification using this technique. A typical scenario could be “Receiving calls while listening to music”.